`include "define.v"
module MIOC(    
    input wire memCe,    
    input wire memWr,    
    input wire [31:0] memAddr,  
    input wire [31:0] wtData,    
    input wire [31:0] ramRdData,    
    input wire [31:0] ioRdData,    
    output reg [31:0] rdData,        
    output reg ramCe,    
    output reg ramWe,    
    output reg [31:0] ramAddr,    
    output reg [31:0] ramWtData,    
    output reg ioCe,    
    output reg ioWe,    
    output reg [31:0] ioAddr,    
    output reg [31:0] ioWtData
);


always@(*)        
    if(memCe == `Enable)            
        if(memAddr[31:12] >= 20'h00007)
        begin                
             ioCe = `Enable;              
             ioWe = memWr;                
             ioAddr = memAddr;                
             ramCe = `Disenable;                
             ramWe = `Invalid;                
             ramAddr = `Zero;
			 if(ioWe == `Valid) ioWtData = wtData;
	     	 rdData = ioRdData;             
        end
        else begin                
            ioCe = `Disenable;                
            ioWe = `Disenable;                
            ioAddr = `Zero;                
            ramCe = `Enable;                
            ramWe = memWr;                
            ramAddr = memAddr; 
			if(ramWe == `Valid)	ramWtData = wtData;
            rdData = ramRdData;             
        end
    else begin            
       ioCe = `Disenable;            
       ioWe = `Invalid;            
       ioAddr = `Zero;            
       ramCe = `Disenable;            
       ramWe = `Invalid;            
       ramAddr = `Zero;          
    end
endmodule